	US 12,278,113 B2
	Method for manufacturing semiconductor structure
Zhaohui Wang, Hefei (CN); Wentao Xu, Hefei (CN); and Qiao Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 22, 2022, as Appl. No. 17/950,993.
Claims priority of application No. 202210935724.X (CN), filed on Aug. 4, 2022.
Prior Publication US 2023/0018973 A1, Jan. 19, 2023
Int. Cl. H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)

CPC H01L 21/3086 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76897 (2013.01); H01L 21/7688 (2013.01)]

13 Claims

1. A method for manufacturing a semiconductor structure, comprising:

providing a base and forming a stack layer on the base, wherein the stack layer comprises at least a first sacrificial layer, and a material of the first sacrificial layer comprises an amorphous elemental semiconductor material;

forming second hard mask patterns on the first sacrificial layer through a self-aligned process;

performing a doping process, comprising: doping a region of the first sacrificial layer exposed from gaps between the second hard mask patterns;

removing the second hard mask patterns; and

removing an undoped region of the first sacrificial layer through a selective etching process, so as to form first sacrificial patterns.