US 12,278,104 B2
Multi-layer semiconductor material structure and preparation method thereof
Fengwen Mu, Beijing (CN); Xinhua Wang, Beijing (CN); Sen Huang, Beijing (CN); Ke Wei, Beijing (CN); and Xinyu Liu, Beijing (CN)
Assigned to Institute of Microelectronics of the Chines Academy of Sciences, Beijing (CN)
Appl. No. 17/928,951
Filed by INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES, Beijing (CN)
PCT Filed Sep. 9, 2021, PCT No. PCT/CN2021/117424
§ 371(c)(1), (2) Date Dec. 1, 2022,
PCT Pub. No. WO2022/121408, PCT Pub. Date Jun. 16, 2022.
Claims priority of application No. 202011461767.6 (CN), filed on Dec. 11, 2020.
Prior Publication US 2023/0230831 A1, Jul. 20, 2023
Int. Cl. H01L 21/24 (2006.01); H01L 21/02 (2006.01); H01L 23/373 (2006.01)
CPC H01L 21/02378 (2013.01) [H01L 21/02376 (2013.01); H01L 21/0259 (2013.01); H01L 21/02694 (2013.01); H01L 23/3732 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A multi-layer semiconductor material structure, comprising:
a highly thermally conductive support substrate, and
a crystallized device function layer, which is provided on the highly thermally conductive support substrate, and has a single-crystal surface layer; wherein
the device function layer has a crystal structure, with a single-crystal portion close to the surface and the interface, and a microstructural gradient from single-crystal to poly-crystal from the surface and the interface to a center.