US 12,277,995 B2
Page buffer circuit and memory device including the same
Jin-Young Chun, Suwon-si (KR); Minjae Seo, Suwon-si (KR); and Moosung Kim, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 17, 2022, as Appl. No. 17/988,797.
Claims priority of application No. 10-2021-0158734 (KR), filed on Nov. 17, 2021; and application No. 10-2022-0068256 (KR), filed on Jun. 3, 2022.
Prior Publication US 2023/0154505 A1, May 18, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/20 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1069 (2013.01); G11C 7/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a memory cell;
a bit line connected to the memory cell;
a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line;
a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter;
a third transistor connected among the first transistor, the second transistor, and a ground power; and
a control circuit for operating the first transistor and the second transistor at least once during a period in which the third transistor is turned on, wherein at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged comprises the period the third transistor is turned on.