US 12,277,991 B2
Memory device with reset voltage control
Ali Taghvaei, Kanata (CA); and Atul Katoch, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 25, 2022, as Appl. No. 17/824,738.
Claims priority of provisional application 63/310,528, filed on Feb. 15, 2022.
Prior Publication US 2023/0260558 A1, Aug. 17, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/20 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 7/12 (2013.01); G11C 7/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device including:
a memory cell;
a precharge circuit coupled to the memory cell through a bit line, the precharge circuit to set a voltage of the bit line to a first voltage level;
a reset voltage control circuit including a transistor coupled to the bit line to set the voltage of the bit line to a second voltage level, the transistor operating as a diode; and
a logic control circuit coupled to the precharge circuit and the reset voltage control circuit, the logic control circuit to:
cause the reset voltage control circuit to set the voltage of the bit line to the second voltage level during a reset phase,
cause the precharge circuit to set the voltage of the bit line to the first voltage level during a precharge phase after the reset phase, and
determine that data stored by the memory cell is a first state, in response to the voltage of the bit line during a sensing phase having a third voltage level, wherein the second voltage level is between the first voltage level and the third voltage level.