| CPC G11C 7/1012 (2013.01) [G11C 7/06 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/1096 (2013.01); G11C 8/08 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
a first mux transistor and a first control transistor coupled between a sense amplifier and ground, and commonly connected at a first node;
a first shared gate transistor connecting a first bit line to the first node;
a second shared gate transistor connecting a second bit line to the first node;
a first memory cell connected to the first bit line; and
a second memory cell connected to the second bit line, wherein the first memory cell and the second memory cell share a first word line transistor gated by a first word line.
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