| CPC G11C 5/063 (2013.01) [G11C 5/025 (2013.01); H10B 63/34 (2023.02); H10B 63/84 (2023.02)] | 20 Claims |
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1. A semiconductor memory device comprising:
a bit line extending in a first direction;
multiple word lines each extending at least in a second direction perpendicular to the first direction, the multiple word lines being stacked in a third direction perpendicular to the first direction and the second direction;
a source region; and
a cell array including multiple cell blocks arranged in the second direction,
wherein each of the cell blocks includes
a first selection transistor with a gate connected to a first selection gate line,
a second selection transistor with a gate connected to a second selection gate line,
a first local bit line connectable to the bit line through the first selection transistor, the first local bit line extending in the third direction,
a second local bit line connectable to the bit line through the second selection transistor, the second local bit line extending in the third direction,
a local source line connectable to the source region, the local source line extending in the third direction,
multiple first memory cells connected in parallel between the first local bit line and the local source line, and
multiple second memory cells connected in parallel between the second local bit line and the local source line, and
wherein each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series,
a gate of the first cell transistor corresponds to one of the multiple word lines,
each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series,
a gate of the second cell transistor corresponds to one of the multiple word lines,
the first selection gate line extends in the second direction across multiple cell blocks arranged in the second direction, and
the second selection gate line is placed on an opposite side of the first selection gate line with the local source line interposed therebetween, the second selection gate line extending in the second direction across multiple cell blocks arranged in the second direction.
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