US 12,277,987 B2
Error handling device, semiconductor memory device including the same, and error handling method including cross sensing operation
Giseok Kim, Gimpo (KR); Jiyoung Kim, Seoul (KR); Wonjoon Jo, Seoul (KR); Sungho Park, Seoul (KR); Seongook Jung, Seoul (KR); Juhyun Park, Icheon (KR); Seung Ho Lee, Icheon (KR); and Jungchan Lee, Icheon (KR)
Assigned to SK Hynix Inc., Icheon (KR); and Industry-Academic Cooperation Foundation Yonsei University, Seoul (KR)
Filed by SK hynix Inc., Icheon (KR); and Industry-Academic Cooperation Foundation Yonsei University, Seoul (KR)
Filed on Dec. 29, 2022, as Appl. No. 18/148,357.
Claims priority of application No. 10-2022-0038679 (KR), filed on Mar. 29, 2022.
Prior Publication US 2023/0317200 A1, Oct. 5, 2023
Int. Cl. G11C 29/52 (2006.01); G11C 11/419 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 11/419 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An error handling device comprising:
a cross-voltage sense amplifier configured to:
perform a normal sense operation to generate normal sense data by comparing an input voltage and a comparison voltage, and
perform a cross sense operation to generate cross sense data by exchanging and comparing the input voltage and the comparison voltage according to a cross sense signal; and
an error handling circuit configured to identify a location of an error by using the normal sense data and the cross sense data and to correct the error,
wherein the cross-voltage sense amplifier comprises:
a sense amplifier configured to generate an output voltage according to voltage difference between two input voltages provided to a first node and a second node; and
a cross circuit configured to:
provide the input voltage to the first node and the comparison voltage to the second node when the normal sense operation is being performed, and
provide the comparison voltage to the first node and the input voltage to the second node when the cross sense operation is being performed.