US 12,277,986 B2
Apparatuses including and methods for memory subword driver circuits with reduced gate induced drain leakage
Kenji Asaki, Sagamihara (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 14, 2021, as Appl. No. 17/475,206.
Prior Publication US 2023/0078117 A1, Mar. 16, 2023
Int. Cl. G11C 29/50 (2006.01); G11C 11/408 (2006.01)
CPC G11C 29/50004 (2013.01) [G11C 11/4085 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first subword line;
a second subword line coupled to the first subword line by a first common transistor;
wherein, in response to a test mode signal for entering a test mode, a voltage of each of the first and second subword lines is raised to a first voltage from a third voltage and a gate voltage of the first common transistor is raised to a second voltage from a ground voltage, wherein the second voltage is between the first and third voltages and higher than the ground voltage and wherein the gate voltage of the first common transistor remains at the second voltage during the test mode;
a third subword line coupled to an off-state word line voltage through a second common transistor; and
a fourth subword line coupled to the off-state word line voltage through a third common transistor, wherein the off-state word line voltage is below the ground voltage and wherein, in response to the test mode signal, the second and third common transistors are configured to be turned off.