US 12,277,984 B2
Block family error avoidance bin designs addressing error correction decoder throughput specifications
Guang Hu, Mountain View, CA (US); and Nicola Ciocchini, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 8, 2023, as Appl. No. 18/231,514.
Claims priority of provisional application 63/400,586, filed on Aug. 24, 2022.
Prior Publication US 2024/0071547 A1, Feb. 29, 2024
Int. Cl. G11C 29/32 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01); G11C 16/34 (2006.01); G11C 29/50 (2006.01); G11C 29/52 (2006.01); G11C 29/56 (2006.01)
CPC G11C 29/32 (2013.01) [G06F 3/064 (2013.01); G06F 11/076 (2013.01); G11C 16/3404 (2013.01); G11C 16/349 (2013.01); G11C 29/50 (2013.01); G11C 29/52 (2013.01); G11C 29/56008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
maintaining a set of bins, each bin of the set of bins defining a respective grouping of blocks of memory cells in the memory array based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, wherein the set of bins comprises a first bin and a second bin having an associated read window overlap between a first read window defined for the first bin and a second read window defined for the second bin, and wherein the first read window and the second read window correspond to respective valley margins between respective pairs of adjacent threshold voltage distributions;
receiving a request to perform a read operation addressing a block of the grouping of blocks of memory cells assigned to the first bin; and
causing the read operation addressing the block to be performed based on the respective read level offset assigned to the first bin.