US 12,277,983 B2
Semiconductor device
Hiroshi Yoshida, Tokyo (JP); Jun Okuno, Kanagawa (JP); Hiroki Koga, Tokyo (JP); Yusuke Shuto, Kanagawa (JP); and Takeo Tsukamoto, Tokyo (JP)
Assigned to SONY GROUP CORPORATION, Tokyo (JP)
Appl. No. 18/250,486
Filed by SONY GROUP CORPORATION, Tokyo (JP)
PCT Filed Oct. 27, 2021, PCT No. PCT/JP2021/039594
§ 371(c)(1), (2) Date Apr. 25, 2023,
PCT Pub. No. WO2022/102402, PCT Pub. Date May 19, 2022.
Claims priority of application No. 2020-187246 (JP), filed on Nov. 10, 2020.
Prior Publication US 2023/0402119 A1, Dec. 14, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 27/00 (2006.01); H04N 25/73 (2023.01); H10B 41/30 (2023.01); H10B 43/30 (2023.01)
CPC G11C 27/005 (2013.01) [H04N 25/73 (2023.01); H10B 41/30 (2023.02); H10B 43/30 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an input unit configured to input a charge;
a memory unit configured to collect and accumulate a charge from the input unit; and
an output unit configured to detect and output a charge accumulated in the memory unit, wherein
the memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected,
the gate unit is configured to select the accumulation unit that accumulates a charge,
the transfer unit is configured to transfer a charge from the input unit to the accumulation unit selected by the gate unit,
the accumulation unit is configured to accumulate a charge transferred from the transfer unit, and
the transfer unit is further configured to transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit.