CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01)] | 17 Claims |
1. A verifiable one-time programmable, OTP, memory device, the memory device comprising a multiple-time programmable, MTP, memory block and an OTP memory block for storing data, and a memory controller, wherein the memory controller is configured to:
handle write requests and read requests, wherein each write request and read request pertains to writing data to, and reading data from, respectively, a requested position in either the MTP memory block or the OTP memory block,
in response to the write requests, write the data to the requested position in either the MTP memory block or the OTP memory block, and
in response to the read requests, output data as combined from the requested position in the MTP memory block and the requested position in the OTP memory block, regardless if the read requests are for the MTP memory block or the OTP memory block.
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