US 12,277,981 B2
Anti-fuse cell structure, anti-fuse array, operation method for anti-fuse array, and memory
Chuangming Hou, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Apr. 4, 2023, as Appl. No. 18/295,839.
Application 18/295,839 is a continuation of application No. PCT/CN2022/105661, filed on Jul. 14, 2022.
Claims priority of application No. 202210786964.8 (CN), filed on Jul. 4, 2022.
Prior Publication US 2024/0006006 A1, Jan. 4, 2024
Int. Cl. G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/25 (2023.01)
CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01); H10B 20/25 (2023.02)] 15 Claims
OG exemplary drawing
 
1. An anti-fuse cell structure, comprising:
a first anti-fuse transistor, having a first end and a second end;
a first selection transistor, having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor;
a blow enable line, electrically connected to the first end of the first anti-fuse transistor, and configured to perform programming operation on the first anti-fuse transistor;
an active area, extending along a first direction;
a first anti-fuse transistor gate line, extending along a second direction and covering a part of the active area to define the first anti-fuse transistor, wherein the first direction intersects the second direction;
a first selection transistor gate line, extending along the second direction and covering a part of the active area to define the first selection transistor; and
a bit line, electrically connected to the second end of the first selection transistor, located on top of the active area and extending along the first direction,
wherein the blow enable line is located on top of one side of the active area, and the blow enable line is arranged in parallel to the active area and extending along the first direction.