US 12,277,980 B2
Semiconductor storage device
Yasumitsu Sakai, Kanagawa (JP); and Shinichi Moriwaki, Kanagawa (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Kanagawa (JP)
Filed on Dec. 13, 2023, as Appl. No. 18/538,722.
Application 18/538,722 is a continuation of application No. 17/524,535, filed on Nov. 11, 2021, granted, now 11,881,273.
Application 17/524,535 is a continuation of application No. PCT/JP2020/018392, filed on May 1, 2020.
Claims priority of application No. 2019-090697 (JP), filed on May 13, 2019.
Prior Publication US 2024/0112746 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 17/12 (2006.01)
CPC G11C 17/12 (2013.01) [G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor storage device provided with a read only memory (ROM) cell, comprising:
a word line extending in a first direction;
a first bit line extending in a second direction perpendicular to the first direction; and
a power supply line extending in the second direction,
wherein
the ROM cell includes
a first transistor that is a nanowire FET formed above the power supply line,
a second transistor that is a nanowire FET formed above the first transistor, channel portions of the first and second transistors overlapping each other as viewed in plan,
gates of the first and second transistors are connected to the word line,
one of the first and second transistors is provided between the first bit line and the power supply line, and
first data is stored in the ROM cell depending on the presence or absence of connection between a source of the one of the first and second transistors and the power supply line or the presence or absence of connection between a drain of the one of the first and second transistors and the first bit line.