US 12,277,978 B2
Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices
James Fitzpatrick, Laguna Niguel, CA (US); Phong Sy Nguyen, Livermore, CA (US); Dung Viet Nguyen, San Jose, CA (US); and Sivagnanam Parthasarathy, Carlsbad, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 16, 2024, as Appl. No. 18/636,901.
Application 18/636,901 is a continuation of application No. 17/841,096, filed on Jun. 15, 2022, granted, now 11,984,171.
Claims priority of provisional application 63/221,886, filed on Jul. 14, 2021.
Prior Publication US 2024/0265979 A1, Aug. 8, 2024
Int. Cl. G11C 7/00 (2006.01); A63B 24/00 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3404 (2013.01) [A63B 24/0075 (2013.01); G11C 16/26 (2013.01); A63B 2024/0068 (2013.01); A63B 2024/0093 (2013.01); A63B 2220/836 (2013.01); A63B 2230/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a wordline;
a plurality of bitlines; and
a plurality of memory cells connected to the wordline and the plurality of bitlines;
wherein the plurality of memory cells are configured as a plurality of groups;
wherein each of the groups is configured to provide a plurality of planes of bit storage;
wherein each of the planes is configured to store a codeword of an error correction code technique, the codeword having a predetermined size; and
wherein responsive to a determination based on a bit error rate of the plurality of memory cells, the device is reconfigurable to generate redundant data from codewords stored in first planes provided by the plurality of memory cells and store the redundant data in at least one second plane provided by the plurality of memory cells.