US 12,277,977 B2
ONON sidewall structure for memory device and method for making the same
Chen-Ming Huang, Tainan (TW); Wen-Tuo Huang, Tainan (TW); Yu-Hsiang Yang, Tainan (TW); Yu-Ling Hsu, Tainan (TW); Wei-Lin Chang, Changhua (TW); Chia-Sheng Lin, Tainan (TW); ShihKuang Yang, Tainan (TW); Yu-Chun Chang, Tainan (TW); Hung-Ling Shih, Tainan (TW); Po-Wei Liu, Tainan (TW); and Shih-Hsien Chen, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on May 13, 2024, as Appl. No. 18/662,709.
Application 18/662,709 is a continuation of application No. 18/337,498, filed on Jun. 20, 2023, granted, now 12,009,033.
Application 18/337,498 is a continuation of application No. 17/459,330, filed on Aug. 27, 2021, granted, now 11,854,621, issued on Dec. 26, 2023.
Prior Publication US 2024/0296890 A1, Sep. 5, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 41/35 (2023.01)
CPC G11C 16/10 (2013.01) [H01L 29/6656 (2013.01); H01L 29/7841 (2013.01); H10B 41/35 (2023.02); G11C 16/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a gate structure over a substrate; and
a sidewall spacer located on a side surface of the gate structure, the sidewall spacer comprising a first oxide layer over the side surface of the gate structure, a first nitride layer over the first oxide layer, a second oxide over the first nitride layer, and a second nitride layer over the second oxide layer, wherein the first oxide layer extends between a bottom surface of the first nitride layer and the substrate, and the second oxide layer extends between a bottom surface of the second nitride layer and the substrate.