| CPC G11C 16/0483 (2013.01) [H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 8 Claims |

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1. A memory array comprising strings of memory cells, comprising:
a vertical stack comprising alternating insulative tiers and conductive tiers;
channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, the channel-material strings in a vertical region projecting laterally outward compared to a portion of the channel-material strings that is immediately-above the vertical region and compared to a portion of the channel-material strings that is immediately-below the vertical region; and
the conductive tiers comprising conductive gate lines that are individually operatively laterally proximate the channel-material strings in individual of the conductive tiers, the conductive gate lines comprising part of some of the memory cells in that individual conductive tier, one of the conductive gate lines that is in the vertical region being vertically thicker than another of the conductive gate lines that is immediately-above the vertical region and another of the conductive gate lines that is immediately-below the vertical region.
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