| CPC G11C 16/0433 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/08 (2013.01)] | 18 Claims |
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1. A method, comprising:
receiving a command to perform a read operation on a first memory cell that comprises a first transistor having a floating gate for storing a logic state of the first memory cell and a second transistor coupled with the floating gate of the first transistor, the first memory cell coupled with a word line, wherein the word line is coupled with a gate of the first transistor and a gate of the second transistor;
grounding a source line, the source line coupled with the first transistor of the first memory cell, a second memory cell, and a third memory cell, wherein grounding the source line comprises applying a first voltage to deactivate the second memory cell and applying a second voltage to activate the third memory cell, the first voltage different from the second voltage;
applying, as part of the read operation, a third voltage to a digit line that is connected with the second transistor;
applying, as part of the read operation, a fourth voltage to the word line that is coupled with the gate of the first transistor to activate the first transistor, wherein an amplitude of the fourth voltage is less than zero based at least in part on the first transistor being a p-type transistor; and
determining the logic state stored by the first memory cell based at least in part on a signal on the digit line during at least a portion of a duration that the source line is grounded.
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