	US 12,277,970 B2
	Compensating non-ideality of a neuromorphic memory device
Benedikt Kersting, Lüdinghausen (DE); Athanasios Vasilopoulos, Kilchberg (CH); Manuel Le Gallo-Bourdeau, Horgen (CH); Julian Röttger Büchel, Zurich (CH); and Abu Sebastian, Adliswil (CH)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 19, 2023, as Appl. No. 18/337,214.
Prior Publication US 2024/0420762 A1, Dec. 19, 2024
Int. Cl. G11C 11/54 (2006.01); G11C 13/00 (2006.01)

CPC G11C 13/0069 (2013.01) [G11C 11/54 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01)]

20 Claims

1. A method for compensating non-ideality of a neuromorphic memory device, the neuromorphic memory device comprising a crossbar array, the crossbar array comprising wordlines and bitlines and resistive memory elements coupled between the wordlines and the bitlines at junctions formed by the wordlines and the bitlines, the crossbar array comprising an initial block of one or more wordline segments of respective wordlines, referred to as initial wordlines, and one or more bitline segments of respective bitlines, referred to as initial bitlines, wherein the resistive memory elements of the initial block are programmed to represent array values; the device being configured for applying a set of encoding inputs to the initial wordlines for performing dot products; the method comprising:

performing at least one of: wordline expansion or bitline expansion of the initial block resulting in an expanded block of resistive memory elements,

the wordline expansion comprising adding to each wordline segment of the initial block one or more memory elements of the respective initial wordline resulting in an expanded wordline segment, the adding comprising programming the added memory elements to enable a predefined total conductance in the expanded worldline segment;

the bitline expansion comprising adding to each bitline segment of the initial block one or more memory elements of the respective initial bitline resulting in an expanded bitline segment, the adding comprising programming the added memory elements to generate a predefined offset current in the expanded bitline segment;

applying the set of encoding inputs to the initial wordlines of the expanded block and in case the bitline expansion is performed further applying an additional encoding input to the additional wordlines of the expanded block;

measuring the currents flowing in the bitlines of the expanded block; and

determining the dot products using the measured currents.