| CPC G11C 13/004 (2013.01) [G11C 11/5678 (2013.01); G11C 13/0004 (2013.01); G11C 13/003 (2013.01); H10B 63/84 (2023.02); H10N 70/231 (2023.02); G11C 7/06 (2013.01); G11C 7/1006 (2013.01); G11C 2013/0054 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01); G11C 2213/76 (2013.01)] | 20 Claims |

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1. A method, comprising:
applying a first read voltage to a first set of memory cells and a second read voltage to a second set of memory cells;
updating a first counter based at least in part on applying the first read voltage to the first set of memory cells;
updating a second counter based at least in part on applying the second read voltage to the second set of memory cells; and
reading the first set of memory cells based at least in part on updating the first counter and the second counter.
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