CPC G11C 13/004 (2013.01) [G11C 13/0061 (2013.01); G11C 2013/0054 (2013.01)] | 13 Claims |
1. An in-memory computation device, comprising:
a plurality of computation blocks, receiving a plurality of input signals and generating a plurality of computation results respectively, wherein each of the computation blocks has a plurality of weighting values, and each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values;
a first reference weight block, providing a first reference resistance according to a plurality of reference weighting values and generating a first reference signal according to the first reference resistance and a read voltage; and
an output result generator, coupled to the computation blocks and the first reference weight block and generating a plurality of output computation results according to the first reference signal and the computation results.
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