| CPC G11C 13/0033 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 29/021 (2013.01); G11C 29/12005 (2013.01)] | 20 Claims |

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1. A memory device, comprising:
a plurality of memory cells, comprising:
a first group of memory cells; and
a second group of memory cells programmed to a predefined logic state of the at least two logic states; and
a memory controller coupled to the plurality of memory cells and configured to carry out a recovery voltage setting operation to set the recovery voltage, the recovery voltage setting operation comprising:
applying a test voltage corresponding to a reading voltage applied to at least one selected memory cell of the first group of memory cells to the memory cells of the second group to assess a logic state thereof;
biasing a corresponding word line to a word line selection voltage lower than the reading voltage;
biasing other word lines to a deselection voltage intermediate between the word line selection voltage and the bit line reading voltage; and
setting the recovery voltage to a voltage based on a last iteration of application of the test voltage to the memory cells of the second group.
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