| CPC G11C 11/4097 (2013.01) [G11C 11/4067 (2013.01); H10B 12/10 (2023.02)] | 20 Claims |
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1. A memory structure, comprising:
a first gate structure, a second gate structure and a third gate structure disposed along a first direction and separated from each other;
a plurality of channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction, each of the plurality of channel bodies has a first end and a second end separated from the first end;
a plurality of source regions separated from each other and having first conductivity types, wherein the plurality of source regions are connected to the first ends of the plurality of channel bodies respectively;
a plurality of drain regions separated from each other and having second conductivity types, wherein the plurality of drain regions are connected to the second ends of the plurality of channel bodies respectively, and the first conductivity type is different from the second conductivity type; and
a plurality of first side plugs disposed along a second direction and extending along a third direction, wherein the plurality of first side plugs are separated from each other and electrically connected to the plurality of source regions and the plurality of channel bodies, and the first direction, the second direction and the third direction are perpendicular to each other,
wherein the first gate structure comprises a plurality of island structures separated from each other, the plurality of island structures are disposed along the second direction and extending along the third direction.
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