| CPC G11C 11/4091 (2013.01) [G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] | 13 Claims |
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1. A sense amplifier capable of performing a logical NOT operation, comprising:
a sense circuit, configured to sense a first voltage of a bit line and a second voltage of an inverse bit line complementary to the bit line;
a first transistor, coupled between a first terminal of the sense circuit and the bit line;
a second transistor, coupled between a second terminal of the sense circuit and the inverse bit line; and
a third transistor, coupled between the bit line and the inverse bit line;
wherein a first memory cell and a second memory cell are respectively controlled by a first word line and a second word line, and wherein the first memory cell and the second memory cell are connected to the bit line;
wherein when the sense amplifier is in an inverse writing state, the sense amplifier writes the second voltage to the second memory cell through a predetermined path, and wherein a first logical state of the first voltage is complementary to a second logical state of the second voltage.
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