| CPC G11C 11/2257 (2013.01) [G11C 5/063 (2013.01); G11C 11/2255 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 51/40 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a cell region in which a plurality of memory cells are disposed in a first direction and a second direction, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting each other, wherein each of the plurality of memory cells comprises:
a first active region and a second active region arranged in the first direction,
a channel layer connected to the first active region and the second active region, and
a ferroelectric layer and a gate electrode layer surrounding the channel layer; and
a peripheral circuit region in which are disposed:
a plurality of sense amplifiers connected to the plurality of memory cells via a plurality of bit lines,
a row decoder connected to the plurality of memory cells via a plurality of word lines, and
a control logic controlling the plurality of sense amplifiers and the row decoder,
wherein, in two or more memory cells stacked in a third direction perpendicular to the upper surface of the substrate, the first active regions of the two or more memory cells are connected to each other and the second active regions of the two or more memory cells are connected to each other, and
the first active region in each of the plurality of memory cells receives a reference voltage in common with each other of the plurality of memory cells,
the second active region in each of the plurality of memory cells is connected to one of the plurality of bit lines, and
the gate electrode layer in each of the plurality of memory cells is connected to one of the plurality of word lines.
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