| CPC G11C 11/161 (2013.01) [H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] | 7 Claims |

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1. A memory device, comprising:
a memory pillar including a bottom electrode, a magnetic random-access memory stack above the bottom electrode and a top electrode above the magnetic random-access memory stack;
a bottom electrode contact structure located below, and in direct mechanical contact with and electrically connected to, the bottom electrode;
a first portion of an encapsulation layer located on opposite sidewalls of the bottom electrode, on opposite sidewalls of the magnetic random-access memory stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer located above a second dielectric layer;
a metal cap located above an uppermost surface and opposite sidewalls of a top portion of the top electrode, wherein the metal cap is in contact with an uppermost surface of the first portion of the encapsulation layer;
a second conductive interconnect above a top surface of the metal cap, the second conductive interconnect wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap, and
a first conductive interconnect located below, and in direct mechanical contact with and electrically connected to, the bottom electrode contact structure.
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