an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit;

wherein the input circuit is connected to an input terminal and is configured to control a level of a first node in response to an input signal input from the input terminal;

the first control circuit is connected to the first node, a second node, and a first clock signal terminal, and is configured to control a level of the second node under control of the level of the first node and a first clock signal provided by the first clock signal terminal;

the output circuit is connected to an output terminal and is configured to output an output signal from the output terminal under control of the level of the second node;

the output noise reduction circuit is connected to the output terminal and is configured to reduce noise at the output terminal under control of the level of the first node; and

the reset circuit is directly connected to a total reset terminal, a third node, and a first voltage terminal and is configured to turn off the output noise reduction circuit in response to a total reset signal provided by the total reset terminal, wherein the total reset signal is an invalid level in a first operation stage, and the total reset signal comprises at least one period of valid level in a second operation stage,

the output noise reduction circuit is further directly connected to the third node and is configured to output an invalid level of the output signal at the output terminal in response to the level of the third node;

wherein the shift register unit further comprises a sixth control circuit,

wherein the sixth control circuit is connected to the total reset terminal, the first voltage terminal, and the first node, and the sixth control circuit is configured to reset the first node under control of the total reset signal provided by the total reset terminal.