US 12,277,906 B2
Pixel driving circuit, display panel and display device
Xuliang Zhao, Beijing (CN); Jianchao Zhu, Beijing (CN); and Lujiang Huangfu, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/029,829
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Apr. 7, 2022, PCT No. PCT/CN2022/085538
§ 371(c)(1), (2) Date Mar. 31, 2023,
PCT Pub. No. WO2023/193181, PCT Pub. Date Oct. 12, 2023.
Prior Publication US 2024/0363071 A1, Oct. 31, 2024
Int. Cl. G09G 3/3241 (2016.01)
CPC G09G 3/3241 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/06 (2013.01); G09G 2320/0209 (2013.01); G09G 2320/0693 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display substrate, comprising a plurality of pixel driving circuits for driving a light emitting element, wherein the pixel driving circuit comprises:
a driving sub-circuit, a first terminal of the driving sub-circuit being coupled to a power supply line;
a compensation sub-circuit, respectively coupled to a scanning line, a control terminal of the driving sub-circuit, and a second terminal of the driving sub-circuit; configured to control to connect or disconnect the control terminal and the second terminal of the driving sub-circuit under the control of the scanning line;
a coupling sub-circuit, a first terminal of the coupling sub-circuit being coupled to the control terminal of the driving sub-circuit;
a storage sub-circuit, a first terminal of the storage sub-circuit being coupled to a second terminal of the coupling sub-circuit;
a data writing-in sub-circuit, respectively coupled to a second terminal of the storage sub-circuit, a data line, and a reset line; configured to control to connect or disconnect the second terminal of the storage sub-circuit and the data line under the control of the reset line;
a first reset sub-circuit, respectively coupled to the reset line, an initialization signal line, the control terminal of the driving sub-circuit, and the second terminal of the coupling sub-circuit; configured to, under the control of the reset line, control to connect or disconnect the initialization signal line and the control terminal of the driving sub-circuit and control to connect or disconnect the initialization signal line and the second terminal of the coupling sub-circuit;
a first maintenance sub-circuit, respectively coupled to the scanning line, the second terminal of the coupling sub-circuit, and the initialization signal line; configured to control to connect or disconnect the second terminal of the coupling sub-circuit and the initialization signal line under the control of the scanning line; and
a second maintenance sub-circuit, respectively coupled to the a first control line, a reference signal line and the second terminal of the storage sub-circuit; configured to control to connect or disconnect the reference signal line and the second terminal of the storage sub-circuit under the control of the first control line;
wherein the pixel driving circuit comprises a first capacitor and a third transistor, and the first capacitor includes a first electrode plate and a second electrode plate oppositely arranged, and the first electrode plate is multiplexed as a gate electrode of the third transistor;
the display substrate includes:
a plurality of data lines, wherein the data line includes at least a portion extending along the first direction, an orthographic projection of the data line on a base substrate of the display substrate and an orthographic projection of the first electrode plate on the base substrate are arranged along a second direction, the first direction intersects the second direction;
a plurality of first shielding patterns, wherein at least part of an orthographic projection of the first shielding pattern on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first electrode plate on the base substrate; and/or
at least part of the orthographic projection of the first shielding pattern on the base substrate is located between the orthographic projection of the data line on the base substrate and an orthographic projection of the second electrode plate on the base substrate;
wherein the pixel driving circuit further comprises a second capacitor, the second capacitor includes a third electrode plate and a fourth electrode plate oppositely arranged, the third electrode plate is coupled to the second electrode plate;
the third electrode plate and the second electrode plate are arranged along the first direction;
at least part of the orthographic projection of the first shielding pattern on the base substrate is located between the orthographic projection of the data line on the base substrate and an orthographic projection of the third electrode plate on the base substrate and/or,
at least part of the orthographic projection of the first shielding pattern on the base substrate is located between the orthographic projection of the data line on the base substrate and an orthographic projection of the fourth electrode plate on the base substrate.