US 12,277,905 B2
Pixel and display device including pixel
Keunwoo Kim, Seongnam-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Jun. 25, 2024, as Appl. No. 18/753,689.
Application 18/753,689 is a continuation of application No. 18/234,089, filed on Aug. 15, 2023, granted, now 12,039,932.
Application 18/234,089 is a continuation of application No. 17/961,098, filed on Oct. 6, 2022, granted, now 11,749,196, issued on Sep. 5, 2023.
Claims priority of application No. 10-2022-0026761 (KR), filed on Mar. 2, 2022.
Prior Publication US 2024/0347005 A1, Oct. 17, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/32 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/32 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0257 (2013.01); G09G 2320/045 (2013.01); G09G 2330/021 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A pixel comprising:
a first switching transistor including a first terminal to which a bias power supply voltage is applied, a second terminal connected to a first node, and a gate terminal to which a light emitting element initialization signal is applied;
a second switching transistor including a first terminal connected to the first node, a second terminal connected to a second node, and a gate terminal to which the light emitting element initialization signal is applied;
a driving transistor including a first terminal connected to the second node, a second terminal connected to a third node that is connected to the first node, and a gate terminal;
a storage capacitor including a first electrode connected to a fourth node and a second electrode connected to the gate terminal of the driving transistor;
a holding capacitor including a first electrode to which a first power supply voltage is applied and a second electrode connected to the fourth node;
a light emitting element including a first terminal electrically connected to the driving transistor and a second terminal to which a second power supply voltage that is lower than the first power supply voltage is supplied,
wherein the bias power supply voltage having a first voltage level is applied to the second node via the first and second switching transistors when the first and second switching transistors are turned on, and
wherein the bias power supply voltage having a second voltage level is applied to the third node via the first switching transistor when the first and second switching transistors are turned on.