| CPC G09G 3/3233 (2013.01) [G09G 3/2096 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/02 (2013.01); G09G 2320/043 (2013.01)] | 17 Claims |
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1. A display panel comprising:
a plurality of data lines configured to receive data signals;
a plurality of gate lines configured to receive a gate pulse;
a plurality of pixel circuits, each of the plurality of pixel circuits being connected to one of the plurality of data lines and one of the plurality of gate lines;
a first gate driving circuit configured to supply the gate pulse to first ends of the plurality of gate lines;
a second gate driving circuit configured to supply the gate pulse to second ends of the plurality of gate lines;
a first feedback line connected to an output node of the first gate driving circuit;
a second feedback line connected to an output node of the second gate driving circuit;
a first clock line configured to supply a clock signal to a clock node of the first gate driving circuit; and
a second clock line configured to supply the clock signal to a clock node of the second gate driving circuit,
wherein the first and second gate driving circuits are configured to:
double-feed the gate pulse to a corresponding gate line among the plurality of gates lines from opposite ends of the corresponding gate line, and
in response to one of the first and second gate driving circuits operating abnormally, single-feed the gate pulse to the corresponding gate line from only a remaining one of the first and second gate driving circuits,
wherein the first gate driving circuit and the second gate driving circuit are configured to:
receive the clock signal when the gate pulse is double-fed to the corresponding gate line, and
receive a direct current voltage at the clock node of one of the first gate driving circuit and the second gate driving circuit when the gate pulse is single-fed to the corresponding gate line,
wherein the clock signal swings between a gate-on voltage and a gate-off voltage, and
wherein the direct current voltage maintains the gate-off voltage while the gate pulse is single-fed to the corresponding gate line.
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