| CPC G09G 3/32 (2013.01) [G09G 3/3225 (2013.01); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0866 (2013.01); G09G 2310/0267 (2013.01); G09G 2320/045 (2013.01); G09G 2330/021 (2013.01)] | 18 Claims |
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1. A gate driving circuit, comprising:
a first pull-down circuit controlled by a Q node and configured to transmit a low voltage to a first output node;
a first pull-up circuit controlled by a QB1 node and configured to transmit a high voltage to the first output node;
a QB2 node control circuit configured to transmit a voltage of the QB1 node to a QB2 node;
a second pull-down circuit controlled by the Q node and configured to transmit the low voltage to a second output node; and
a second pull-up circuit controlled by the QB2 node and configured to transmit a high voltage of a first output clock signal to the second output node,
wherein a pulse width of a signal output to the first output node is the same as a pulse width of the Q node,
wherein, in synchronization with a falling pulse edge of a start clock signal from the high voltage to the low voltage, the high voltage is output as the signal output to the first output node,
wherein a pulse width of a signal output to the second output node is the same as a pulse width of the first output clock signal, and
wherein, in synchronization with a rising pulse edge of the first output clock signal from the low voltage to the high voltage, the first output clock signal is output as the signal output to the second output node.
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