| CPC G09G 3/20 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0267 (2013.01); G09G 2330/021 (2013.01)] | 20 Claims |
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1. A gate driver including a plurality of stages, each of the plurality of stages comprising:
a control circuit which controls a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal, and a second clock signal;
a carry output circuit which outputs a carry signal in response to the voltage of the first node and the voltage of the second node;
a first enable node controlling circuit which controls a voltage of a first enable node in response to the carry signal, a first enable signal, and a first inverted enable signal;
a first masking circuit which controls a voltage of a third node in response to the voltage of the second node and the voltage of the first enable node;
a first gate output circuit which outputs an initialization gate signal in response to the voltage of the first node and the voltage of the third node;
a second enable node controlling circuit which controls a voltage of a second enable node in response to the carry signal, a second enable signal, and a second inverted enable signal;
a second masking circuit which controls a voltage of a fourth node in response to the voltage of the second node and the voltage of the second enable node; and
a second gate output circuit which outputs a compensation gate signal in response to the voltage of the first node and the voltage of the fourth node.
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