US 12,277,760 B2
Analyzing data using a hierarchical structure
Paul Dlugosch, Eagle, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 31, 2022, as Appl. No. 17/977,113.
Application 17/977,113 is a continuation of application No. 15/728,216, filed on Oct. 9, 2017, granted, now 11,488,378.
Application 15/728,216 is a continuation of application No. 14/087,904, filed on Nov. 22, 2013, granted, now 9,785,847.
Application 14/087,904 is a continuation of application No. 12/943,551, filed on Nov. 10, 2010, granted, now 8,601,013.
Claims priority of provisional application 61/353,546, filed on Jun. 10, 2010.
Prior Publication US 2023/0154176 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/44 (2018.01); G06F 9/28 (2006.01); G06F 9/445 (2018.01); G06F 9/448 (2018.01); G06F 9/455 (2018.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01); G06N 20/00 (2019.01); G06V 10/94 (2022.01)
CPC G06V 10/94 (2022.01) [G06F 9/28 (2013.01); G06F 9/44521 (2013.01); G06F 9/4498 (2018.02); G06F 9/45516 (2013.01); G06F 15/17312 (2013.01); G06F 15/7871 (2013.01); G06F 15/7885 (2013.01); G06N 20/00 (2019.01)] 23 Claims
OG exemplary drawing
 
1. A system comprising:
multiple parallel machines arranged in a hierarchical structure, including a first parallel machine in a first level of the hierarchical structure and a second parallel machine in a second level of the hierarchical structure, each parallel machine comprising:
a data input port configured to receive data;
a programming interface configured to provide instructions to processing circuitry;
an output port configured to transmit output from the processing circuitry, wherein a first parallel machine output port is coupled to a second parallel machine data input port; and
the processing circuitry configured by the instructions from the programming interface to produce the output from the data, the output based on a pattern present in the data;
wherein the multiple parallel machines are configured to:
provide a first settling time for the first parallel machine to process first input data and, in response, generate first pattern detection output;
transfer the first pattern detection output from the first parallel machine to the second parallel machine after the first settling time;
provide a second settling time for the second parallel machine to process the first pattern detection output from the first parallel machine and, in response, generate a pattern detection result and feedback information for the first parallel machine;
transfer the feedback information from the second parallel machine to the first parallel machine; and
using the feedback information, update a processing routine of the first parallel machine for processing subsequent input data;
wherein a maximum data rate of the first input data and the subsequent input data is based on the settling times and a number of levels of the hierarchical structure.