| CPC G06N 3/08 (2013.01) [G06N 3/045 (2023.01); G06N 3/063 (2013.01)] | 20 Claims |
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1. A neural processor circuit, comprising:
a tensor access operation circuit coupled to a system memory external to the neural processor circuit, the tensor access operation circuit configured to:
select, based on a mode signal, an operation mode to access the system memory in one of two mutually exclusive modes;
indirectly access, in response to the selected operation mode including a first mode of the two mutually exclusive modes, at least a region of a source tensor in the system memory based on a first index for referencing a first index tensor in the system memory generated by a first circuit using a source index provided to the first circuit in the first mode;
indirectly access, in response to the selected operation mode including a second mode of the two mutually exclusive modes, at least the region of the source tensor in the system memory based on crop descriptors generated by a second circuit and used for computation of an indirect source index, wherein the crop descriptors are generated by the second circuit receiving as input a second index for referencing a second index tensor, the second index is generated by a third circuit using the source index provided to the third circuit in the second mode, the source tensor comprising one or more source components having a rank; and
map the one or more source components into an input tensor having another rank;
a data processor circuit coupled to the tensor access operation circuit, the data processor circuit configured to store an output version of the input tensor; and
at least one neural engine circuit coupled to the data processor circuit, the at least one neural engine circuit configured to:
receive, from the data processor circuit, the output version of the input tensor as a plurality of units of input data; and
perform at least one convolution operation on the plurality of units of the input data to generate output data.
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