US 12,277,419 B2
Apparatuses, methods, and systems for instructions to convert 16-bit floating-point formats
Alexander F. Heinecke, San Jose, CA (US); Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); Menachem Adelman, Haifa (IL); Christopher J. Hughes, Santa Clara, CA (US); Evangelos Georganas, San Mateo, CA (US); Zeev Sperber, Zichron Yackov (IL); Amit Gradstein, Binyamina (IL); and Simon Rubanovich, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 24, 2020, as Appl. No. 17/134,046.
Claims priority of provisional application 63/083,906, filed on Sep. 26, 2020.
Prior Publication US 2022/0100507 A1, Mar. 31, 2022
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30025 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30101 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a source vector comprising N plurality of 16-bit half-precision floating-point elements, and a destination vector to store N plurality of 16-bit bfloat floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the source vector from 16-bit half-precision floating-point format to 32-bit full-precision floating point format, and then convert each of the elements from the 32-bit full-precision floating point format to 16-bit bfloat floating-point format in parallel by a respective converter circuit of a plurality of converter circuits of the execution circuitry, and store each converted 16-bit bfloat floating-point element into a corresponding location of the destination vector;
decode circuitry to decode the fetched single instruction into a decoded single instruction and
the execution circuitry to respond to the decoded single instruction as specified by the opcode.