US 12,277,405 B1
Divider, processor, and calculation apparatus
Danyang Wang, Guangdong (CN); Yun Zhai, Guangdong (CN); Zhijun Fan, Guangdong (CN); and Zuoxing Yang, Guangdong (CN)
Assigned to SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 18/857,330
Filed by SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Jun. 17, 2024, PCT No. PCT/CN2024/099491
§ 371(c)(1), (2) Date Oct. 16, 2024,
PCT Pub. No. WO2025/039692, PCT Pub. Date Feb. 27, 2025.
Claims priority of application No. 202311072282.1 (CN), filed on Aug. 24, 2023.
Int. Cl. G06F 7/53 (2006.01); G06F 5/01 (2006.01); G06F 7/50 (2006.01); G06F 7/535 (2006.01)
CPC G06F 7/535 (2013.01) [G06F 5/01 (2013.01); G06F 7/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A divider for performing a division operation between a dividend and a divisor, comprising:
at least one shift circuit comprising a first-stage shift circuit, wherein the first-stage shift circuit is configured to shift a received first operand to left to generate a second operand, and the first operand initially input into the divider is generated from the dividend;
at least one selection circuit comprising a first-stage selection circuit, wherein the first-stage selection circuit is configured to select a first preset multiple of a third operand from preset multiples of the third operand, the first preset multiple of the third operand is as a fourth operand, the third operand is generated from the divisor, the second operand is greater than or equal to the first preset multiple of the third operand, the second operand is less than a second preset multiple of the third operand, and the second preset multiple is greater than the first preset multiple by one; and
at least one operational circuit comprising a first-stage operational circuit, wherein a first input terminal of the first-stage operational circuit is connected to an output terminal of the first-stage shift circuit, a second input terminal of the first-stage operational circuit is connected to an output terminal of the first-stage selection circuit, and the first-stage operational circuit is configured to calculate an OR operation result of a difference and the first preset multiple, the difference is the difference from subtracting the fourth operand from the second operand, and the OR operation result is as a fifth operand.