	US 12,277,379 B2
	Method and system for generating layout diagram including wiring arrangement
Fong-Yuan Chang, Hsinchu (TW); Chin-Chou Liu, Jhubei (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Meng-Kai Hsu, Xinfeng Township (TW); Pin-Dai Sue, Tainan (TW); Po-Hsiang Huang, Tainan (TW); Yi-Kan Cheng, Taipei (TW); Chi-Yu Lu, New Taipei (TW); and Jung-Chou Tsai, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/448,149.
Application 18/448,149 is a continuation of application No. 16/299,973, filed on Mar. 12, 2019, granted, now 11,775,727.
Claims priority of provisional application 62/644,306, filed on Mar. 16, 2018.
Prior Publication US 2023/0394219 A1, Dec. 7, 2023
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 119/18 (2020.01)

CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2119/18 (2020.01)]

20 Claims

1. A method of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium, the method comprising:

placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer;

determining whether the first candidate location results in a group of cut patterns which violates a design rule, the cut patterns of the group having a first arrangement of spatial relationships amongst each other; and

temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule, the correction adjusting the first arrangement of spatial relationships.