US 12,277,374 B2
Synthesis placement bounds based on physical timing analysis
David Castle, Irvine, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Aug. 20, 2021, as Appl. No. 17/408,261.
Claims priority of provisional application 63/068,615, filed on Aug. 21, 2020.
Prior Publication US 2022/0058328 A1, Feb. 24, 2022
Int. Cl. G06F 30/392 (2020.01); G06N 20/00 (2019.01); G06F 111/04 (2020.01)
CPC G06F 30/392 (2020.01) [G06N 20/00 (2019.01); G06F 2111/04 (2020.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
identifying, based on a first synthesizing of an integrated circuit layout representation, a plurality of integrated circuit layout endpoints;
identifying, based on a plurality of layout feature vectors each representing a layout endpoint of the plurality of integrated circuit layout endpoints, a plurality of integrated circuit layout clusters, each integrated circuit layout cluster comprising a unique subset of integrated circuit layout endpoints of the plurality of integrated circuit layout endpoints; and
applying, using a processor and based on a subsequent synthesizing of the integrated circuit layout representation, placement bounds to the integrated circuit layout representation, wherein the placement bounds are applied based on the plurality of integrated circuit layout clusters.