| CPC G06F 30/347 (2020.01) [G06F 30/3953 (2020.01)] | 20 Claims |
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1. A method for fabricating a digital circuit using a field programmable gate array (FPGA), the FPGA comprising (1) a plurality of programmable logic blocks for implementing a plurality of digital logics and (2) a plurality of programmable routing resources for connecting or disconnecting inputs and outputs of the plurality of programmable logic blocks, the method comprising:
designing the FPGA with a computer-aided design system implementing a routing tool, the designing step further including:
via an input device of the computer-aided design system, receiving a netlist representing a target digital circuit to be fabricated, the netlist having source nodes, sink nodes, and a plurality of intermediate nodes at fixed positions,
via a design router of the computer-aided design system, determining routing interconnections between the source nodes and the sink nodes,
via a display device of the computer-aided design system, continuously displaying the interconnections and a routing utilization while the interconnections are being determined, and
via the design router, making adjustments to the routing interconnections, based on user feedback on the interconnections and routing utilization displayed at the display device; and
configuring, based on the routing interconnections determined in the designing step, the plurality of programmable routing resources, such that the inputs and outputs of the plurality of programmable logic blocks are selectively connected or disconnected to form the target digital circuit,
wherein the design router converges to an interconnection solution in which all signals are routed while achieving close to an optimal performance allowed by the fixed positions of the source nodes and the sink nodes,
wherein the design router includes a negotiated-congestion routing component which allows the interconnections to share the intermediate nodes and to negotiate for these intermediate nodes, the routing component using a congestion cost which increases relative to increases in congestion in the intermediate nodes,
wherein the congestion cost is a function of a base cost of a respective intermediate node, a historical cost of the respective intermediate node, a present usage cost of the respective intermediate node, and a usage and a capacity of the respective intermediate node, where the historical cost is an accumulated cost of the respective intermediate node, and
wherein the design router performs a historical cost function for the respective intermediate node that is based on the base cost of the respective intermediate node in order to force the design router to include intermediate nodes of a base cost that are lower than a baseline cost.
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