	US 12,277,372 B2
	Multi-cycle test generation and source-based simulation
Peter Wohl, Williston, VT (US); and John A. Waicukauski, Tualatin, OR (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Apr. 14, 2022, as Appl. No. 17/721,264.
Claims priority of provisional application 63/175,595, filed on Apr. 16, 2021.
Prior Publication US 2022/0335187 A1, Oct. 20, 2022
Int. Cl. G06F 30/3308 (2020.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01)

CPC G06F 30/3308 (2020.01) [G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01)]

20 Claims

1. A method, comprising:

determining clock data of a circuit design, the circuit design including clock signals and cells, wherein determining the clock data comprises:

determining a first clock signal pair from the clock signals; and

determining a disturb cell of the cells based on the first clock signal pair, wherein the disturb cell is electrically coupled to a first clock signal of the first clock signal pair, the disturb cell is electrically coupled to a second cell of the cells, and the second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell;

generating a first test pattern based on the clock data; and

outputting the first test pattern to a memory.