US 12,277,349 B2
Internal clock signaling
Liang Yu, Boise, ID (US); Luigi Pilolli, L'Aquila (IT); and Biagio Iorio, Luco dei Marsi (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 29, 2024, as Appl. No. 18/622,132.
Application 18/622,132 is a continuation of application No. 17/464,868, filed on Sep. 2, 2021, granted, now 11,960,764.
Prior Publication US 2024/0241673 A1, Jul. 18, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 1/04 (2006.01); G06F 1/3234 (2019.01)
CPC G06F 3/0659 (2013.01) [G06F 1/04 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 1/3275 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
selecting a primary ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice groups of a memory device;
setting the primary R/B # pin to a first status;
receiving by at least one memory die among a plurality of memory dice within a first memory dice group, signaling indicative of performance of a memory access of the first memory dice group of the plurality of memory dice groups;
receiving, by the at least one memory die among a plurality of memory dice within a second memory dice group, signaling indicative of performance of the memory access involving the second memory dice group among the plurality of memory dice groups; and
concurrently initiating a first internal clocking signal and a second internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the first memory dice group and the second memory dice group among the plurality of memory dice groups, wherein the concurrently initiated first internal clocking signal and the second internal clocking signal are associated with timing of operations performed by the plurality of memory dice groups.