US 12,277,348 B2
Memory system and information processing system
Takeshi Nakano, Kawasaki Kanagawa (JP); Akihiko Ishihara, Yokohama Kanagawa (JP); Shingo Tanimoto, Yokohama Kanagawa (JP); Yasuaki Nakazato, Kamakura Kanagawa (JP); Shinji Maeda, Kawasaki Kanagawa (JP); Minoru Uchida, Yokohama Kanagawa (JP); Kenji Sakaue, Yokohama Kanagawa (JP); Koichi Inoue, Yokohama Kanagawa (JP); Yosuke Kino, Yokohama Kanagawa (JP); Takumi Sasaki, Kawasaki Kanagawa (JP); Mikio Takasugi, Kawasaki Kanagawa (JP); Kouji Saitou, Tokyo (JP); Hironori Nagai, Kamakura Kanagawa (JP); Shinya Takeda, Yokohama Kanagawa (JP); Akihito Touhata, Yokohama Kanagawa (JP); Masaru Ogawa, Ebina Kanagawa (JP); and Akira Aoki, Yokosuka Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Nov. 3, 2023, as Appl. No. 18/501,943.
Application 18/501,943 is a continuation of application No. 17/185,104, filed on Feb. 25, 2021, granted, now 11,853,599.
Claims priority of application No. 2020-062221 (JP), filed on Mar. 31, 2020; and application No. 2020-173167 (JP), filed on Oct. 14, 2020.
Prior Publication US 2024/0061620 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of controlling a non-volatile memory, the method comprising:
writing log data to a first memory, the log data including a history of commands for controlling the non-volatile memory;
writing the log data from the first memory to a second memory;
detecting an error in the non-volatile memory that occurs when one of the commands is executed; and
writing the log data from the second memory to the non-volatile memory in response to detecting the error in the non-volatile memory.