US 12,277,347 B2
Apparatus and methods for back-to-back state machine controller bus operations
Kei Akiyama, Yokohama (JP); Iris Lu, Fremont, CA (US); Yoshito Katano, Fujisawa (JP); and Tai-Yuan Tseng, Milpitas, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Sep. 13, 2023, as Appl. No. 18/466,085.
Prior Publication US 2025/0085895 A1, Mar. 13, 2025
Int. Cl. G06F 3/06 (2006.01); G11C 7/08 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01); G11C 7/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory structure comprising non-volatile memory cells; and
a first processor configured to provide a plurality of sets of commands to a second processor to perform memory operations on the non-volatile memory cells, the second processor configured to execute the sets of commands and provide a control signal to the first processor, the first processor further configured to provide the sets of commands to the second processor based on a status of the control signal,
wherein the second processor is further configured to control the status of the control signal so that the second processor executes sets of commands with no idle time between consecutive sets of commands.