a plurality of memory planes, each memory plane including a plane core and a corresponding specific set of resources, each respective memory plane being operable to perform (i) foreground operations using at least one of the specific set of resources of the corresponding memory plane and resources of the plane core of the corresponding memory plane and (ii) background operations using the resources of the plane core of the corresponding memory plane;

an input/output (I/O) interface to receive memory commands from a host addressed to one or more memory planes of the plurality of memory planes;

a status control circuit generating status bits corresponding to each memory plane of the plurality of memory planes, the status bits indicating (i) one of a busy state and a ready state of the specific set of resources used by a foreground operation of the corresponding memory plane and (ii) one of an in operation state and an idle state of the resources of the plane core of the corresponding memory plane; and

control circuits operably coupled with the I/O interface, the status control circuit and the plurality of memory planes, to execute memory operations using the plurality of memory planes;

wherein in the execution of a memory operation using one or more memory planes in the plurality of memory planes, the control circuits generate a plurality of status bits, in the status control circuit, corresponding to each memory plane in the plurality of memory planes; and

wherein the control circuits execute, or deny execution of, memory operations of a received memory command in response to combinations of the received memory command and the plurality of status bits in the status control circuit, including a first type of memory command executed, or denied execution, dependent on combinations of the busy and ready states and the in operation and idle states of all the memory planes in the plurality of memory planes, and a second type of memory command addressed to a particular memory plane executed, or denied execution, independent of combinations of the busy and ready states and the in operation and idles states of memory planes in the plurality of memory planes other than the particular memory plane.