US 12,277,342 B2
Controller and method of performing internal operation thereof
Ku Ik Kwon, Gyeonggi-do (KR); Byong Woo Ryu, Gyeonggi-do (KR); Su Ik Park, Gyeonggi-do (KR); Jin Won Jang, Gyeonggi-do (KR); and Yong Joon Joo, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 20, 2021, as Appl. No. 17/506,366.
Claims priority of application No. 10-2021-0074697 (KR), filed on Jun. 9, 2021.
Prior Publication US 2022/0398039 A1, Dec. 15, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controller that controls a memory device, comprising:
a host interface suitable for determining a remaining resource index and outputting a task scheduling instruction when a data throughput determined based on data inputted/outputted between a host and the controller is lower than a maximum throughput required under a current workload pattern; and
a processor suitable for:
selecting, in response to the task scheduling instruction, at least one internal task having a highest priority among a plurality of internal tasks based on the remaining resource index, resource consumption indexes of the respective plurality of internal tasks, and the current workload pattern, wherein priorities of the at least one of the plurality of internal tasks selected vary depending on the current workload pattern, and
performing the selected at least one internal task having the highest priority under the current workload pattern while performing an input/output task,
wherein the current workload pattern includes a data type and a data attribute of the data inputted/outputted between the host and the controller,
wherein the data type includes a read pattern and a write pattern,
wherein the data attribute includes a sequential pattern and a random pattern.