US 12,277,327 B2
Configurable storage resource usage through a multi-phase data processing pipeline for data storage efficiency
Sreeram Vasudevan, Singapore (SG); George Chen Kaidi, Singapore (SG); Li Hua Lim, Singapore (SG); and Vipul Jain, Singapore (SG)
Assigned to PAYPAL, INC., San Jose, CA (US)
Filed by PAYPAL, INC., San Jose, CA (US)
Filed on Aug. 21, 2023, as Appl. No. 18/453,229.
Prior Publication US 2025/0068342 A1, Feb. 27, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0631 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a non-transitory memory; and
one or more hardware processors coupled to the non-transitory memory and configured to read instructions from the non-transitory memory to cause the system to perform operations comprising:
receiving data designated for a storage in a data store associated with the system;
determining a first reduction in a data size for the storage of the data based on a data conversion operation for a first type of the data;
determining a second reduction in a storage resource usage for the storage of the data based on a data deduplication operation for the data with other data stored by the data store;
determining a third reduction in a time period for the storage of the data based on a storage level operation and an access frequency to the data;
converting the data for the storage based on the first reduction, the second reduction, and the third reduction; and
storing the converted data in the data store.