| CPC G06F 3/0622 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] | 15 Claims |
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1. A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table update size, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the at least one NV memory element comprising a plurality of blocks, the method comprising:
utilizing the memory controller to receive a set of first commands from a host device through a transmission interface circuit of the memory controller, receive a set of first data with a first active block among the plurality of blocks according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block, wherein the set of first commands indicate that writing the set of first data into the memory device is requested, and the set of first data is written into the first active block;
determining a selected table update size among multiple predetermined table update sizes according to at least one predetermined rule, wherein the multiple predetermined table update sizes represent multiple table entry counts, respectively; and
updating at least one logical-to-physical (L2P) address mapping table in the NV memory according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, for use of data accessing, wherein a table entry count of the set of P2L table entries is equal to the selected table update size.
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