a memory array comprising a plurality of memory cells grouped in rows and columns of memory cells, each of the memory cells comprising a memory unit adapted to store data, a current source comprising a first switching device and a current generator device, and a second switching device;

a plurality of input lines, each connected to the second switching devices in a respective row and adapted to transmit an input signal to the second switching device in the row;

a plurality of output lines, each associated with a respective column of the memory unit; and

a plurality of current controllers, each connected to the current generator devices in a respective column of the memory cells through a current control line and adapted to set a level of current generated by the current generator devices in the respective column of the memory cells, the levels of the currents generated by the respective current generator devices differing by substantially a factor of 2^j, where j is an integer;

wherein the second switching device in each of the columns of memory cells is adapted to connect or disconnect the current source in the memory cell to the output line associated with the column depending on the input signal received from the input line, and the first switching device in each of the memory cells is adapted to permit or prevent current flow from the current generator device depending on the data stored in the memory unit in the memory cell.