US 12,277,288 B2
Interface circuit and memory controller
Fu-Jen Shih, New Taipei (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Jun. 26, 2023, as Appl. No. 18/213,907.
Claims priority of application No. 112102152 (TW), filed on Jan. 18, 2023.
Prior Publication US 2024/0241785 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/041 (2006.01); G06F 11/10 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0418 (2013.01) [G06F 11/1068 (2013.01); G06F 11/3037 (2013.01); G06F 13/1673 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An interface circuit, comprising:
a signal processing circuit, configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises:
a plurality of signal processing devices; and
a monitor and calibration module, comprising:
a plurality of monitor circuits, configured to monitor at least one of an amplitude, a frequency and a jitter in at least one of the reception signal and the transmission signal to generate a monitored result corresponding to the at least one of the amplitude, the frequency and the jitter in the at least one of the reception signal and the transmission signal and to monitor at least one of a power supplying voltage and a ground voltage to generate a monitored result corresponding to the at least one of the power supplying voltage and the ground voltage in a monitor and calibration procedure;
a plurality of calibration circuits, coupled to the signal processing devices and respectively configured to perform a calibration operation on at least one of the signal processing devices in the monitor and calibration procedure to adjust a characteristic value of the at least one of the signal processing devices; and
a compensation control mechanism operation logic, coupled to the monitor circuits and the calibration circuits and configured to collect the monitored results from the monitor circuits and sequentially generate a calibration control signal corresponding to each calibration circuit based on the monitored results to respectively control the corresponding calibration circuit to perform the calibration operation on the at least one of the signal processing devices in response to the calibration control signal,
wherein the compensation control mechanism operation logic comprises a plurality of hardware circuits, and the hardware circuits comprise:
a compensation control mechanism selection circuit, comprising a plurality of compensation control mechanism selection logics and configured to select a compensation control mechanism corresponding to the monitored results based on the monitored results and set the compensation control mechanism as a currently-operating compensation control mechanism to control at least one of the hardware circuits to operate in compliance with the currently-operating compensation control mechanism.