US 12,277,255 B2
Secure semiconductor and system design
David D. Moser, Haymarket, VA (US); Daniel L. Stanley, Warrenton, VA (US); Joshua C. Schabel, Apex, NC (US); Tate J. Keegan, Merrimack, NH (US); and Sheldon L. Grass, Chester, NH (US)
Assigned to BAE Systems Information and Electronic Systems Integration Inc., Nashua, NH (US)
Appl. No. 17/907,020
Filed by BAE SYSTEMS Information and Electronic Systems Integration Inc., Nashua, NH (US)
PCT Filed Mar. 24, 2022, PCT No. PCT/US2022/021750
§ 371(c)(1), (2) Date Sep. 22, 2022,
PCT Pub. No. WO2023/182993, PCT Pub. Date Sep. 28, 2023.
Prior Publication US 2024/0202375 A1, Jun. 20, 2024
Int. Cl. G06F 21/76 (2013.01); G06F 30/347 (2020.01)
CPC G06F 21/76 (2013.01) [G06F 30/347 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A secure semiconductor device, comprising:
a data port;
a network on chip (NoC) module;
a processor communicatively coupled to the NoC module, the processor configured to generate an access key;
a communication interface operatively coupled to the processor and to the data port, the communication interface configured to
enable communication access to and from the NoC module via the data port in response to a presence of the access key, and
disable the communication access to and from the NoC module via the data port in response to an absence of the access key; and
an electronic field-programmable gate array (eFPGA) configuration module;
a programmable logic block configured to operate in a boundary scan mode; and
a clock configured to disable the boundary scan mode of the programmable logic block in response to an absence of FPGA configuration data stored in the eFPGA configuration module.