| CPC G06F 16/24542 (2019.01) [G06F 16/24539 (2019.01)] | 30 Claims |
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1. A system comprising:
at least one hardware processor; and
a memory storing instructions that cause the at least one hardware processor to perform operations comprising:
receiving a query, the query including a set of statements for performing the query;
performing a lookup operation on a shadow cache, provided by a stored plan cache, for an exact match based on information from a compilation context, the stored plan cache including a regular cache and the shadow cache, the regular cache including a first set of stored query plans and the shadow cache including a second set of stored query plans;
in response to the lookup operation finding the exact match of a particular query plan in the shadow cache:
performing a validation process on the particular query plan for determining a cache hit on the shadow cache;
in response to determining the cache hit, performing a program building process to update the particular query plan with additional information for executing the particular query plan;
performing a compilation process to compile an updated program of the updated particular query plan;
determining that the updated particular query plan is cacheable based at least in part on the compilation process;
registering the updated particular query plan as a new entry in the shadow cache; and
sending the updated program to an execution node for executing the updated particular query plan.
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